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Consumer demand for sophisticated real-time multimedia and mobile communications, enabled by continued advances in semiconductor technology, have led to a rapid increase in embedded system complexity. However, limitations in today's design methods and tooling hamper the designer's ability to deliver next-generation applications in a timely and cost-effective manner. This presentation examines advances in CAD and co-design tools by reviewing the co-design methodology adopted by CoWare and the SystemC approach to hardware synthesis. In addition, we report our experience of the Handel-C hardware compiler and the Ptolemy design and simulation environment tools. While these tools improve productivity by facilitating hardware and software concurrent engineering and raise abstraction levels in order to manage implementation complexity they fail to address the broader issue of system architectural design. We contend that a structured top-down approach is needed in order to develop robust systems from the diverse range of ASIC, programmable logic, and microprocessor platform options now available to engineers. We conclude by presenting our ideas on system architecture and methodology, which we believe will fill this system design gap.
This presentation gives a brief introduction to virtual prototyping applied to electronic systems and takes a look at our current direction. For some time the Centre for VLSI and Computer Graphics has been using high-level design techniques in the development of 3D graphics ASICs and FPGAs. This has led to a research thread in the area of prototyping of electronic systems. Based on our early work with an algorithmic-level development platform targeted at graphics, DPX has been developed to provide a high-level electronic prototyping environment using C++. We are extending this to provide a virtual environment for conceptual prototyping.
CoWare is a true Hardware-Software Co-Design tool that enables the user to specify a system-level description in a super-set of C. Exploration of various partitioning strategies of functional blocks between hardware and software can be successively tried and refined. The program automatically creates the software and hardware to implement the interfaces between blocks, prior to logic synthesis using conventional synthesis tools. CoWare via RAL ships with ARM7 processor target that is fully supported by additional Design Signoff Models and routes to fabrication via Alcatel Microelectronics. Similar flows for FPGAs will be supported when commercially available.
Software and hardware design has become more efficient as development tools and simulators have improved in functionality. However, the software/hardware integration phase of embedded system development has increased in duration owing to the increased complexity and speed of modern embedded processors. The presentation describes one particular solution to this challenge. This is the use of a combination of debug tools that make use of the dynamic data acquisition facilities that microprocessor manufacturers have recently implemented. It is hoped that a demonstration will be included.
Parallel computing is still a necessity for those embedded systems such as target-tracking radar where throughput and/or latencies are otherwise too great. Product lifecycles of over ten years and microprocessor lifecycles of less than five years imply that a portable, scalable design is paramount. PPF (Pipelined Processor Farms) is a generic approach to top-down design of embedded parallel systems whose lessons remain relevant but which is being adapted to increasing hardware multiplicity. This presentation will review the recent PSTESPA research project that aimed to systematize the construction and performance analysis of parallel computing systems with homogeneous processors. The presentation will look forward to the two-level multicomputer in which the processor interconnect is separated from the compute engine which might over time be choice of RISC, DSP, FPGA, or in part ASIC. It is proposed that the parallel software component is a way of encapsulating algorithms, parallel structure, and varying hardware granularity in a way convenient for system prototyping/codesign. PSTESPA as a project was interested in toolkits and it remains important to provide an infrastructure for testing at the system level.
Although the Microchip PIC is very popular with hobbyists and experimenters, and its Harvard architecture has attractions for introductory teaching of microprocessors, it is not widely used for practical work relating to such teaching because the actions of the processor are hidden behind the IC's ports. Since 1998, Southampton University staff and third-year project students have been developing SoftPIC - an FPGA-based hardware emulation of a PIC. In AY 2000/1 this will be used to give first-year undergraduates practical experience of the behaviour of a simple RISC micro. The presentation will address the philosophies behind SoftPIC, some of the aims of the laboratory programme in which it will be used, and aspects of the practical realisation of a SoftPIC experimentation platform.
Last updated 2000 October 9.
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