Workshop 2005: Provisional Programme


Last update: 6th September 2005

Day 1 - Wednesday 7th September

Activity

Location

4.30pm - 7.00pm

Registration

Department of Electronic Systems Engineering, Main Foyer, Square 1

7.00pm 8.15pm

Evening meal

Cafe Vert, Square 3

8.30pm 9.30pm

Evening presentation - activity to be confirmed

Department of Electronic Systems Engineering, Seminar Room 1N1.4.1

Evening

Social gathering

Student Union Bar, Square 3

 

Day 2 - Thursday 8th September

Activity

Location

7.30am 8.30am

Breakfast

"Food on 3", Square 3

8.45am 9.20am

Registration

Department of Electronic Systems Engineering, Seminar Room 1N1.4.1

9.20am - 9.30am

Chairperson's welcome

Department of Electronic Systems Engineering, Seminar Room 1N1.4.1

9.30am 10.45am

Oral presentations

 

K. Barratt and P. Coulton, Department of Communication Systems, Lancaster University, UK, "Experiences of a Problem Solving Approach to Teaching FPGA Programming"

 

E. Jolly and M. Fleury, Department of Electronic Systems Engineering, University of Essex, "Design of a Real-time Hough Transform on Configurable Logic"

 

T. O'Shea and I. Grout, Department of Electronic and Computer Engineering, University of Limerick, Ireland, "Prototyping and Evaluating DSP Functions in MATLAB(R)/SIMULINK(R): A Sigma-Delta Analogue Signal Generation Evaluation System "

 

Department of Electronic Systems Engineering, Seminar Room 1N1.4.1

 

10.45am 11.15am

Morning coffee break

 Department of Electronic Systems Engineering, Seminar Room 1N1.4.1

11.15am 12.30pm

Oral presentations

 

D. Carline, P. Coulton an C. Carr, Department of Communication Systems, Lancaster University, UK, "Teaching DSP Techniques on FPGAs Using an Algorithmic Approach in Handel-C"

 

K. Cheng and M. Fleury, Department of Electronic Systems Engineering, University of Essex, "Design of a Network Security Devices with Hardware Compilation and FPGA Development System -Educational Implications"

 

M. Burbidge, Special Interests Group project "kick-off" meeting

 

Department of Electronic Systems Engineering, Seminar Room 1N1.4.1

 

12.30pm 1.30pm

Buffet Lunch and demonstrations/roadshow

 

RAL Roadshow

 

Demonstration - University of Essex

 

Demonstration - University of Limerick, "Sigma-Delta Signal Generator Prototyping System"

 

Department of Electronic Systems Engineering, Seminar Room 1N1.4.1

1.30pm 1.55pm

EEUG AGM

Department of Electronic Systems Engineering, Seminar Room 1N1.4.1

1.55pm 2.10pm

Simon Steiner, Higher Education Academy Engineering Subject Centre update

Department of Electronic Systems Engineering, Seminar Room 1N1.4.1

2.10pm 2.35pm

RAL Microelectronics Support Centre update

Department of Electronic Systems Engineering, Seminar Room 1N1.4.1

2.35pm - 3.00pm

Tea and close

Department of Electronic Systems Engineering, Seminar Room 1N1.4.1