Workshop 2002 Abstracts

 


 

Group Design Project Using Xilinx FPGA

 

Project/Funding:         Course Unit EENG28010 and EENG28050, Department funded

Authors:                    Erik Dagless, Dave Milford, Phil Churn, Department of Electrical and Electronic Engineering, University of Bristol

Devices:                    XC4010E 84 pin

ECAD used;              Xilinx Foundation version F3.1I

ECAD Support:          Europractice

 

Sumary:

Two years ago we decided to change the group project activity in the 2nd year EE programmes at Bristol University from microprocessor based work to a logic design based task. We had previous experience with a small cohort of students on our CSE programme doing a similar task but now we wanted to work with 70 students and make sure that more (all) students actually implemented a final design on a FPGA.

The task starts with a graded introduction to the Xilinx software which is assessed and marked by computer aided assessment. Then work starts on the group activity designing a system that is specified as a basic system with 3 enhancements. Students choose the enhancements they want to attempt and the marks gained vary accordingly. An initial task for each group is to design, test and write the data sheet for a sub-component of the system. The best sub-component is then used by all the other teams. The final design is tested on a small test rig against a predefined test schedule. Each successful test will gain further marks for the group. The work finishes with a group presentation. The group mark is apportioned to individual members using a peer review system.

How this was carried out last year and plans for enhancing the experience will be reported.

 


 

A Digital ECAD Course with Xilinx

 

 Project/Funding:          Teaching project provided through an academic donation from Xilinx

 Author:                       Jonathan A. Dell , Lecturer in Department of Electronics at York University

 Devices:                     XC4005E FPGA from Xilinx

 ECAD Support:           RAL/Europractice through maintenance contract

 

Summary:

The presentation describes the digital ECAD course undertaken by third year students at York University.  A detailed discussion of the project and its assessment, which runs over seven consecutive weeks, will be given and the beneficial outcomes of the work will be highlighted.  The project involves the design of a simplified four-bit microprocessor and the students have to use hierarchical schematic methods and VHDL to develop solutions for three of the four principal modules.  The architecture of the processor is provided so that the module interfaces are completely specified.  Testing of the component modules is undertaken by making use of the simulation tools and students have to develop a suitable test strategy in each case.  The final objective of the development work is to load the completed design into an FPGA where hardware operation can be observed.  Assessment is undertaken at various stages, initially with the objective of ensuring that students are progressing through the work satisfactorily.  Students keep a lab book, in which they record their comments during the design and their simulation results, this is assessed at the end of the course but can also be used by the demonstrators when giving design assistance.

 


 

TEST ENGINEERING LABORATORIES WITH THE LATTICE MACH-4 CPLD

 

Project/funding:            University of Limerick Teaching & Research Innovation Programme (TRIP)

Authors:                       Ian Grout and Joseph Walsh, Department of Electronic & Computer Engineering, University of Limerick, Limerick, Ireland

Devices:                       Lattice Mach 4 CPLD

ECAD:                         ispDesignEXPERT

ECAD sources:            Lattice Semiconductor

 

Summary:

A project is presented in which the aim is to set-up laboratory exercises in which Integrated Circuit (IC) digital test engineering concepts are to be introduced. This work has recently been commenced and the paper will aim to describe the intended direction for the work and projected outcomes. Today, with the rising digital IC complexities and ever decreasing circuit dimensions, the testing problem for these circuits is increasing in complexity at a time where the need to rapidly reduce costs. For the test engineer today, understanding the design, test and Design for Testability (DfT) aspects needs to be introduced at undergraduate level in both bottom-up and top-down approaches. The aim here is to utilise programmable logic devices (PLDs) to rapidly prototype a range of digital designs using a bottom-up approach. where the design may or may not incorporate circuit faults (modelling circuit faults due to production defects). These circuits will require efficient test program generation in order to determine whether the circuit is fault-free or faulty.

 


 

A FIELD PROGRAMMABLE ANALOGUE SYSTEM SOLUTION

 

Project/funding:        Anadigm               (http://www.anadigm.com)

Author:                    Adrian Bratt, Anadigm

Devices:                  ANx20E04 silicon familyECAD:     AnadigmDesigner®

 

Summary:

The field programmable analogue array (FPAA) is a recent development which allows accurate circuit functions to be quickly synthesised and downloaded to silicon. As a teaching tool for analogue, FPAAs are superb because students are able to design circuits on inexpensive PCs then download the circuit to silicon and make real measurements, bridging the gap between theory and practice in a matter of minutes. The accurate implementation of circuit functions allows students to deal with the fundamentals of analogue design, without having to deal with many of the second and third order effects that can be problematic for beginners.

Anadigm’s AnadigmDesigner®2 PC based Software allows the use of design abstraction to high level functions such as gain stages, oscillators, filters and arbitrary waveform generators to name only a few.  More advanced users can build their own high level modules, either simple or complex, and try them on silicon in a matter of minutes. Design iterations are therefore quick and painless, and can be tuned to the application in a way that is simply not possible with discrete parts. The use of a programmable part also makes interfacing to embedded systems available as a new dimension.

The ANADIGM development system uses SRAM technology, meaning that circuits may be built and downloaded without limit; the development system is very cost effective as a result. The new ANx20E04 silicon family gives a rich matrix of switches, capacitors, opamps, comparators and some very neat high level functions. Most of all it makes analogue electronics fun.

 


 

Xilinx FPGA Reconfiguration using JTAG

 

Project/funding:        Undergraduate electronics teaching laboratory exercises

Author:                    Tim Forcer, Department of Electronics and Computer Science, The University of Southampton

Devices:                   Xilinx XC4000 FPGAs

ECAD:                     Synplify, ModelSim, Xilinx Design Manager

ECAD sources:        RAL, Xilinx University Program

 

Summary:

A JTAG Test Access Port can be realised on Xilinx 4000 series FPGAs, and the IC can be reconfigured via this port.  The information needed to implement these features is difficult to find and scattered across a range of Xilinx documentation.  A straightforward method for incorporating a JTAG TAP has been established, and is used for reconfiguring FPGAs with student designs implemented on a test unit which powers up from PROM.  The accompanying demonstration shows both these features in use

 


 

Hardware/Software Co-Design: a short course for unbelievers

 

A. C. Downton, M. Fleury, R. P. Self, S. J. Sangwine and P. D. Noakes

 

Department of Electronic Systems Engineering, University of Essex, UK

email: {acd|fleum|rpself|sjs|pdn}@essex.ac.uk

 

Abstract

Hardware-Software Co-Design skills are increasingly needed to implement complex distributed embedded systems and systems-on-a-chip for applications in Telecommunications and related fields. Telecommunications and network engineers and computer scientists frequently lack the electronic engineering background to be able to design and implement such systems. Our short course, presented as an option within two different specialist postgraduate degree programmes, and also available direct to industry, has successfully demonstrated that foundation hardware-software co-design skills can be acquired in 2 days by students with limited previous hardware background.

 

Related research project: EPSRC CASE studentship with DERA (now QinetiQ), October 1999 - September 2002. Title: Heterogeneous Client Architectures for Multimedia Computing

Types of devices used: Celoxica RC1000PP and RC100 development boards, Xilinx Virtex and Spartan chips

ECAD used: Celoxica Handel-C and DK1 development environment

Primary source of ECAD support: Celoxica (also available through RAL/Europractice)

 


 

Future Directions in Computer Architectures Curricula: Silicon Compilation for Hardware/Software Co-Design

 

A. C. Downton, M. Fleury, R. P. Self and P. D. Noakes

 

Department of Electronic Systems Engineering, University of Essex, UK

email: {acd|fleum|rpself|pdn}@essex.ac.uk

 

Abstract

Courses in Computer Architectures are increasingly becoming restricted to Electronics and Computer Engineering degrees rather than Computer Science degrees, as Computer Science and Software Engineering expands and student demand increasingly favours software rather than hardware aspects. As a result, a declining proportion of Computing students understand the relationships between software structures and their corresponding hardware implementation and performance - critical issues in embedded systems and hardware-software co-design. In an attempt to redress this balance, we propose a new top-down Computer Architectures course structure that uses silicon compilation as an abstraction to present Computer Architectures in a C-software-oriented format. This approach allows first year undergraduate Computing (and Electronics) students to directly implement and modify minimal processor architectures in a C-language form, without the necessity to explicitly learn assembly language programming or a microprocessor programming environment.

 

Related research project: EPSRC CASE studentship with DERA (now QinetiQ), October 1999 - September 2002. Title: Heterogeneous Client Architectures for Multimedia Computing

Types of devices used: Celoxica RC1000PP and RC100 development boards, Xilinx Virtex and Spartan chips

ECAD used: Celoxica Handel-C and DK1 development environment

Primary source of ECAD support: Celoxica (also available through RAL/Europractice)

 


Last Update: 1st November 2002